This invention relates to a silicon-on-insulator (SOI) device, and more particularly to a SOI transistor having a double gate structure.
As demand on electronic appliance such as portable wireless electronic system is increased recently, the semiconductor device with high integration, high performance, low voltage and low power is interested and developed.
A method for lowering a threshold voltage of a MOSFET is typically used in accomplishing the lower driving voltage. However, the leakage current is increased due to the lowering threshold voltage of a MOSFET so that the electric characteristic of device is degraded. Various method for lowering a threshold voltage are proposed. Among various method, the semiconductor integration technology using a silicon on insulator (SOI) wafer where an oxide layer is sandwiched between two silicon layers is interested. The semiconductor device embodied in the SOI wafer has advantages of high performance due to low junction capacitance, low driving voltage due to low threshold voltage and removal of latch-up due to complete device isolation, as compared with the semiconductor device embodied in a silicon bulk wafer.
FIG. 1 is a sectional view of a SOI transistor embodied in a SOI wafer in the prior art. A SOI wafer 10 including a supporting substrate 11, a buried oxide layer 12 and a silicon layer 13 is prepared and an isolation layer 14 is formed in the silicon layer 13 to be contacted with the buried oxide layer 12. With a conventional process, a gate oxide 15 and a gate 16 are formed over the silicon layer 13 and source and drain regions 17 are formed in the silicon layer 13 at the both sides of the gates 16.
In the above SOI transistor, the source and drain regions 17 are formed to be contacted with the buried oxide layer 12 and the depletion region is removed to reduce the junction capacitance, thereby accomplishing the high performance. Besides, the complete device isolation is accomplished by the buried oxide layer 12 and the isolation layer 14 to prevent the latch-up.
However, the SOI transistor can accomplish the high performance due to the lower threshold voltage as compared with the conventional transistor, but there is a limit to lower the threshold voltage of the SOI transistor.
Recently, a study on a SOI device having a double gate has been progressed, which is fabricated in a SOI wafer and forms two gate in stack. The SOI device having a double gate can further lower the threshold voltage by controlling the voltages applied to two gates.
When the SOI device having a double gate is fabricated, the alignment between two gates becomes an essential factor. Following the lower gate formation, because an upper gate and a source and drain regions are formed in the lower gate, the misalignment between the lower and upper gates is occurred and it increases the capacitance due to the gate overlap, thereby causing the desired phenomenon such as a gate delay.
It is an object of the present invention to provide a SOI device having a double gate being capable of preventing the misalignment between lower and upper gates using a self-aligned contact and a method for fabricating the same.
According to an aspect of the present invention, there is provided to a silicon-on-insulator (SOI) device having a double gate, comprising: a supporting substrate; a first insulating layer formed over the supporting substrate; a first silicon layer formed over the first insulating layer, the first silicon layer including a first impurity region of a first conductivity disposed in a central portion thereof and intrinsic regions disposed at the both sides of the first impurity region; a second insulating layer formed over the first silicon layer; a second silicon layer formed over the second insulating layer, the second silicon layer including a second impurity region of a second conductivity disposed in a central portion thereof over the first impurity region of the first silicon layer and third impurity regions of first conductivities disposed at the both sides of the second impurity region over the respective intrinsic regions of the first silicon layer; a third insulating layer formed over the second impurity region of the second silicon layer; and a polysilicon layer doped with impurity ions of first conductivities, formed over the third insulating layer.
In the SOI device, the first conductivity is N-type and the second conductivity is P-type. On the contrary, the first conductivity is P-type and the second conductivity is N-type.
In the SOI device, the first impurity region of the first silicon layer serves as a lower gate. The first insulating layer serves as a buried oxide layer and is comprised of a thermal oxide layer. The second and third insulating layers serve as a lower gate oxide and an upper gate oxide, respectively. The intrinsic regions prevent the parasitic capacitance from the second impurity region and the first silicon layer. The second impurity region and the third impurity regions serve a channel region and source and drain regions, respectively. The polysilicon layer serves as an upper gate.
There is also provided to a method for fabricating a silicon-on-insulator (SOI) device having a double gate, comprising the steps of: preparing a supporting substrate and a device substrate; forming an insulating layer over the supporting substrate; implanting oxygen ions into the device substrate to form a first oxide layer within the device substrate; implanting hydrogen ions into the device substrate below the first oxide layer to form an ion implanting layer below the first oxide layer and to define a first silicon layer and a second silicon layer over and below the first oxide layer, respectively; bonding the device substrate and the supporting substrate to contact the insulating layer with the first silicon layer; removing a portion of the device substrate including the ion implanting layer until the second silicon layer is exposed; implanting impurity ions of a first conductivity into the first silicon layer; pattering the first and second silicon layers and the first oxide layer; forming a second oxide layer over the second silicon layer; implanting impurity ions of a second conductivity into the second silicon layer; forming a polysilicon layer doped with an impurity ions of first conductivities over the second oxide layer; pattering the polysilicon layer and the second oxide layer to form an upper gate having a width smaller than the lower gate; implanting impurity ions of a first conductivity into the first silicon layer using the upper gate as a barrier to form intrinsic regions at the both sides of the upper gate in the first silicon layer and a lower gate between the intrinsic regions; and implanting impurity ions of a first conductivity into the second silicon layer using the upper gate as a barrier to form source and drain regions at the both sides of the upper gate in the second silicon layer.